1. Field of the Invention
The present invention relates to contact interfaces on the surface of semiconductor substrates and methods of forming the same. More particularly, the present invention relates to forming silicide interfaces for use with thin film devices and backend integrated circuit (“IC”) testing devices.
2. Background of Related Art
In the processing of integrated circuits, electrical contact must be made to isolated active-device regions formed within a semiconductor substrate, such as a silicon wafer. Such active-device regions may include p-type and n-type source and drain regions used in the production of NMOS, PMOS, and CMOS structures for production of DRAM chips and the like. The active-device regions are connected by conductive paths or lines which are fabricated above an insulative or dielectric material covering a surface of the semiconductor substrate. To provide electrical connection between the conductive path and the active-device regions, openings in the insulative material are generally provided to enable a conductive material to contact the desired regions, thereby forming a “contact.” The openings in the insulative material are typically referred to as “contact openings.”
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are goals of the computer industry. However, as components become smaller and smaller, tolerances for all semiconductor structures (such as circuitry traces, contacts, dielectric thickness, and the like) become more and more stringent. In fact, each new generation of semiconductor device technology has seen a reduction in contact size of, on average, about 0.7 times. Further, the reduction in size of integrated circuits also results in a reduction in the height of the integrated circuits.
Of course, the reduction in contact size (i.e., diameter) has resulted in a greatly reduced area of contact between the active-device regions and the conductive material. Regardless of the conductive material used to fill these small contact openings to form the contacts (such as tungsten or aluminum), the interface between the conductive material and active-device region must have a low resistance.
Various methods have been employed to reduce the contact resistance at the interface between the conductive material and active-device region. One such method includes the formation of a metal silicide contact interface atop the active-device region within the contact opening prior to the application of the conductive material into the contact opening. A common metal silicide material formed is cobalt silicide (CoSix, wherein x is predominately equal to 2) generated from a deposited layer of cobalt. Cobalt silicide is preferred for shallow junctions of thin film structures because it forms very smooth, fine grained silicide, and will not form tightly bonded compounds with arsenic or boron atoms used in the doping of shallow junctions.
FIGS. 27-31 illustrate a common method of forming a cobalt silicide layer on an active-device region of a thin film semiconductor device. FIG. 27 illustrates an intermediate structure 400 comprising a semiconductor substrate 402 with a polysilicon layer 404 thereon, wherein the polysilicon layer 404 has at least one active-device region 406 formed therein with a thin dielectric layer 408, such as tetraethyl orthosilicate—TEOS, disposed thereover. The thin dielectric layer 408 must be as thin as possible to reduce the height of the thin film semiconductor device. A contact opening 412 is formed, by any known technique, such as patterning and etching, in the thin dielectric layer 408 to expose a portion of the active-device region 406, as shown in FIG. 28. A thin layer of cobalt 414 is applied over the thin dielectric layer 408 and the exposed portion of the active-device region 406, as shown in FIG. 29. A high temperature anneal step is conducted in an inert atmosphere to react the thin cobalt layer 414 with the active-device region 406 in contact therewith which forms a cobalt silicide layer 416, as shown in FIG. 30. However, dielectric materials, such as TEOS—tetraethyl orthosilicate, BPSG—borophosphosilicate glass, PSG—phosphosilicate glass, and BSG—borosilicate glass, and the like, are generally porous. Thus, the thin dielectric layer 408 has imperfections or voids which form passages through the thin dielectric layer 408. Therefore, when the high-temperature anneal is conducted, cobalt silicide also forms in these passages. The cobalt silicide structures in the passages are referred to as patches 418, as also shown in FIG. 30. When the nonreacted cobalt layer 414 is removed to result in a final structure 422 with a cobalt silicide layer 416 formed therein, as shown in FIG. 31, the patches 418 also form conductive paths between the upper surface of the thin dielectric layer 408 which can cause shorting and current leakage on IC backend testing devices which leads to poor repeatability and, thus, poor reliability of the data from the testing devices.
Although such voids can be eliminated by forming a thicker dielectric layer 424, the thicher dielectric layer 424 leads to poor step coverage of the cobalt material 426 in bottom corners 428 of the contact opening 412, as shown in FIG. 32. The poor step coverage is caused by a build-up of cobalt material 426 on the upper edges 432 of the contact opening 412 which causes shadowing of bottom corners 428 of the contact openings 412. The result is little or no cobalt material 426 deposited at the bottom corners 428 of the contsct opening 412 and consequently an inefficient silicide contact formed after annealing.
Step coverage can be improved by using filtering techniques, such as physical collimated deposition and low-pressure long throw techniques, which are used to increase the number of sputtered particles contacting the bottom of the contact opening. However, such filtering techniques are costly and the equipment is difficult to clean. Furthermore, filtering techniques also reduce the deposition rate of the cobalt material which reduces product throughput and, in turn, increases the cost of the semiconductor device. Moreover, using a thick dielectric layer is counter to the goal of reducing semiconductor device size. Finally, a thick dielectric layer eliminates the ability of the structure to be used as a backend IC probing device since the contacts are too small and too deep in the dielectric material. This is a result of dielectric material not being scalable. As device geometries get smaller, the thickness of the dielectric cannot be reduced without the potential of shorting and/or formation of patches. Thus, contact size must be increased to allow probe tips to fit in contacts, which is counter to the goal of reducing semiconductor device size.
Thus, it can be appreciated that it would be advantageous to develop a technique and a contact interface which is free from patch formations, while using inexpensive, commercially available, widely practiced semiconductor device fabrication techniques and equipment without requiring complex processing steps.